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2k x 8 reprogrammable registered prom cy7c245a cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-04007 rev. *e revised august 17, 2006 features ? windowed for reprogrammability ? cmos for optimum speed/power ? high speed ? 15-ns address set-up ? 10-ns clock to output ? low power ? 330 mw (commercial) for -25 ns ? 660 mw (military) ? programmable synchronous or asynchronous output enable ? on-chip edge-triggered registers ? programmable asynchronous register (init ) ? eprom technology, 100% programmable ? slim, 300-mil, 24-pin plastic or hermetic dip ?5v 10% v cc , commercial and military ? ttl-compatible i/o ? direct replacement for bipolar proms ? capable of withstanding greater than 2001v static discharge functional description the cy7c245a is a high-perfo rmance, 2k x 8, electrically programmable, read-only memory packaged in a slim 300-mil plastic or hermetic dip. the ceramic package may be equipped with an erasure window; when exposed to uv light the prom is erased and can then be reprogrammed. the memory cells utilize proven eprom floating-gate technology and byte-wide intelligent programming algorithms. the cy7c245a replaces bipolar devices and offers the advan- tages of lower power, reprogrammability, superior perfor- mance and high programming yield. the eprom cell requires only 12.5v for the supervoltage, and low current requirements allow gang programming. the eprom cells allow each memory location to be tested 100%, because each location is written into, erased, and repeatedly exercised prior to encap- sulation. each prom is also tested for ac performance to guarantee that after customer programming the product will meet ac specification limits. the cy7c245a has an asynchronous initialize function (init ). this function acts as a 2049th 8-bit word loaded into the on-chip register. it is user programmable with any desired word, or may be used as a pr eset or clear function on the outputs. init is triggered by a low level, not an edge. logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd v cc a 8 a 9 init cp o 7 o 6 o 4 o 5 o 3 programmable array multiplexer 15 8-bit edge- register triggered o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 cp cp e /e s e /e s 28 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 11 12 19 a 5 v cc gnd a 6 a 7 o 3 o 1 o 0 18 o 4 o 5 nc a 0 a 4 a 3 a 10 nc nc nc init e /e s o 7 o 6 a 2 a 1 cp o 2 a 8 init initialize word programmable a 9 programmable multiplexer dq c a 10 address decoder a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 8 a 9 a 10 a 7 column address row address dip top view lcc/plcc (opaque only) top view selection guide 7c245a-15 7c245a-18 7c245a-25 7c245a-35 unit minimum address set-up time 15 18 25 35 ns maximum clock to output 10 12 12 15 ns maximum operating current standard commercial 120 120 90 90 ma military 120 120 120 ma
cy7c245a document #: 38-04007 rev. *e page 2 of 13 operating modes the cy7c245a is a cmos electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar ttl fusible link proms. the cy7c245a incorporates a d-type, master-slave register on chip, reducing the cost and size of pipelined micropro- grammed systems and applicat ions where accessed prom data is stored temporarily in a register. additional flexibility is provided with a programmable synchronous (e s ) or asynchronous (e ) output enable and asynchronous initial- ization (init ). upon power-up the state of the outputs will depend on the programmed state of the enable function (e s or e ). if the synchronous enable (e s ) has been programmed, the register will be in the set condition causing the outputs (o 0 ?o 7 ) to be in the off or high-impedance state. if the asynchronous enable (e ) is being used, the outputs will come up in the off or high-impedance state only if the enable (e ) input is at a high logic level. data is read by applying the memory location to the address inputs (a 0 ?a 10 ) and a logic low to the enable input. the stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. at the next low-to-high transiti on of the clock (cp), data is transferred to the slave flip-f lops, which drive the output buffers, and the accessed data will appear at the outputs (o 0 ?o 7 ). if the asynchronous enable (e ) is being used, the outputs may be disabled at any time by switching the enable to a logic high, and may be returned to the active state by switching the enable to a logic low. if the synchronous enable (e s ) is being used, the outputs will go to the off or high-impedan ce state upon the next positive clock edge after the synchronous enable input is switched to a high level. if the synchronous enable pin is switched to a logic low, the subsequent positive clock edge will return the output to the active state. following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next low-to-high transition of the cl ock. this unique feature allows the cy7c245a decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. system timing is simplified in that the on-chip edge triggered register allows the prom clock to be derived directly from the system clock without introducing race conditions. the on-chip register timing requirements are similar to those of discrete registers available in the market. the cy7c245a has an asynchronous initialize input (init ). the initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophis- ticated functions such as a built-in ?jump start? address. when activated, the initialize control input causes the contents of a user-programmed 2049th 8-bit word to be loaded into the on-chip register. each bit is programmable and the initialize function can be used to load any desired combination of 1s and 0s into the register. in t he unprogrammed state, activating init will generate a register clear (all outputs low). if all the bits of the initialize word are programmed, activating init performs a register pr eset (all outputs high). applying a low to the init input causes an immediate load of the programmed initialize word into the master and slave flip-flops of the register, independent of all other inputs, including the clock (cp). the initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (e ) low. erasure characteristics wavelengths of light less than 4000 angstroms begin to erase the 7c245a. for this reason, an opaque label should be placed over the window if the pr om is exposed to sunlight or fluorescent lighting for extended periods of time. the recommended dose for erasure is ultraviolet light with a wavelength of 2537 angstroms for a minimum dose (uv intensity multiplied by exposure time) of 25 wsec/cm2. for an ultraviolet lamp with a 12 mw/cm2 power rating the exposure time would be approximately 35 minutes. the 7c245a needs to be within 1 inch of the lamp during erasure. permanent damage may result if the prom is exposed to high-intensity uv light for an extended period of time. 7258 wsec/cm2 is the recommended maximum dosage. programming information programming support is available from cypress as well as from a number of third-party software vendors. for detailed programming information, including a listing of software packages, please see the prom programming information located at the end of this section. programming algorithms can be obtained from any cypress representative. bit map data programmer address ram data decimal hex contents 00 data . . . . . . . . . 2047 7ff data 2048 800 init byte 2049 801 control byte control byte 00 asynchronous output enable (default state) 01 synchronous output enable
cy7c245a document #: 38-04007 rev. *e page 3 of 13 figure 1. programming pinouts military specifications group a subgroup testing table 1. mode selection mode read or output disable pin function [1] a 10 ?a 4 a 3 a 2 ?a 1 a 0 cp e , e s init o 7 ?o 0 other a 10 ?a 4 a 3 a 2 ?a 1 a 0 pgm vfy v pp d 7 ?d 0 read a 10 ?a 4 a 3 a 2 ?a 1 a 0 v il /v ih v il v ih o 7 ?o 0 output disable a 10 ?a 4 a 3 a 2 ?a 1 a 0 xv ih v ih high z initialize a 10 ?a 4 a 3 a 2 ?a 1 a 0 xv il v il init. byte program a 10 ?a 4 a 3 a 2 ?a 1 a 0 v ilp v ihp v pp d 7 ?d 0 program verify a 10 ?a 4 a 3 a 2 ?a 1 a 0 v ihp v ilp v pp o 7 ?o 0 program inhibit a 10 ?a 4 a 3 a 2 ?a 1 a 0 v ihp v ihp v pp high z intelligent program a 10 ?a 4 a 3 a 2 ?a 1 a 0 v ilp v ihp v pp d 7 ?d 0 program synchronous enable a 10 ?a 4 v ihp a 2 ?a 1 v pp v ilp v ihp v pp high z program initialization byte a 10 ?a 4 v ilp a 2 ?a 1 v pp v ilp v ihp v pp d 7 ?d 0 blank check zeros a 10 ?a 4 a 3 a 2 ?a 1 a 0 v ihp v ilp v pp zeros 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 0 d 1 d 2 gnd v cc d 7 d 6 d 4 d 5 d 3 15 a 9 a 10 v pp vfy pgm 28 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 11 12 19 a 5 v cc gnd a 6 a 7 d 3 d 1 d 0 18 d 4 d 5 nc a 0 a 4 a 3 a 8 nc nc d 7 d 6 a 2 a 1 d 2 a 10 v pp vfy pgm nc a 9 dip top view lcc/plcc (opaque only) top view dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 smd cross reference smd number suffix cypress number 5962-88735 033x cy7c245a-25lmb 5962-88735 04lx cy7c245a-25dmb switching characteristics parameter subgroups t sa 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t co 7, 8, 9, 10, 11 note 1. x = ?don?t care? but not to exceed v cc + 5%.
cy7c245a document #: 38-04007 rev. *e page 4 of 13 maximum ratings [2] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65c to +150c ambient temperature with power applied .................................................. ? 55c to +125c supply voltage to ground potential (pin 24 to pin 12) .................................................? 0.5v to +7.0v dc voltage applied to outputs in high z state .....................................................? 0.5v to +7.0v dc input voltage .................................................? 3.0v to +7.0v dc program voltage (pins 7, 18, 20) ........................... 13.0v uv erasure ................................................... 7258 wsec/cm 2 static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 5v 10% military [3] ? 55c to +125c 5v 10% industrial ?40c to +85c 5v 10% electrical characteristics over the operating range [4,5] parameter description test conditions 7c245a-15 7c245a-18 7c245a-25 7c245a-35 7c245a-45 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma v in = v ih or v il 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 16 ma v in = v ih or v il 0.4 0.4 0.4 v v ih input high level guaranteed input logical high voltage for all inputs 2.0 v cc 2.0 v cc 2.0 v cc v v il input low level guaranteed input logical low voltage for all inputs 0.8 0.8 0.8 v i ix input leakage current gnd < v in < v cc ? 10 +10 ? 10 +10 ? 10 +10 a v cd input clamp diode voltage note 5 i oz output leakage current gnd < v o < v cc output disabled [6] ? 10 +10 ? 10 +10 ? 10 +10 a i os output short circuit current v cc = max., v out = 0.0v [7] ? 20 ? 90 ? 20 ? 90 ? 20 ? 90 ma i cc power supply current v cc = max., i out = 0 ma com?l 120 120 90 ma mil 120 120 v pp programming supply voltage 12 13 12 13 12 13 v i pp programming supply current 50 50 50 ma v ihp input high programming voltage 3.0 3.0 3.0 v v ilp input low programming voltage 0.4 0.4 0.4 v capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf notes 2. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 3. t a is the ?instant on? case temperature. 4. see page 3 of this data sheet for group a subgroup testing information. 5. see the ?introduction to cmos proms? section of the cypress data book for general information on testing. 6. for devices using the synchronous enable, t he device must be clocked after applying these voltages to perform this measuremen t. 7. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds.
cy7c245a document #: 38-04007 rev. *e page 5 of 13 notes 8. applies only when the synchronous (e s ) function is used. 9. applies only when the asynchronous (e ) function is used. ac test loads and waveforms [4, 5] switching characteristics over operating range [4, 5] parameter description 7c245a-15 7c245a-18 7c245a-35 7c245a-25 7c245a-35 unit min. max. min. max. min. max. min. max. min. max. t sa address set-up to clock high 15 18 25 35 45 ns t ha address hold from clock high 0 0 0 0 0 ns t co clock high to valid output 10 12 12 15 25 ns t pwc clock pulse width 10 12 15 20 20 ns t ses e s set-up to clock high 10 10 12 15 15 ns t hes e s hold from clock high 5 5 5 5 5 ns t di delay from init to valid output 15 20 20 20 35 ns t ri init recovery to clock high 10 12 15 20 20 ns t pwi init pulse width 10 12 15 20 25 ns t cos valid output from clock high [8] 15 15 15 20 30 ns t hzc inactive output from clock high [8] 15 15 15 20 30 ns t doe valid output from e low [9] 12 15 15 20 30 ns t hze inactive output from e high [9] 15 15 15 20 30 ns 3.0v 5v output r1 250 ? r2 167 ? 50 pf including jig and scope gnd 90% 10% 90% 10% 5ns 5 ns 5v output 5pf including jig and scope (b) high z load output 2.0v equivalent to: th venin equivalent 100 ? r1 250 ? (a) normal load r2 167 ? all input pulses
cy7c245a document #: 38-04007 rev. *e page 6 of 13 switching waveforms [5] t di t co t doe t hze t hzc t sa t ha t hes t ses t pwc t pwc t pwc t pwc t pwc t pwc t ha t co t cos o 0 ? o 7 a 0 ? a 10 init cp e s e t ri t pwi t hes t ses t hes t ses
cy7c245a document #: 38-04007 rev. *e page 7 of 13 typical dc and ac characteristics 1.4 1.6 1.0 0.8 4.0 4.5 5.0 5.5 6.0 ? 55 25 125 1.2 1.1 1.6 4.0 4.5 5.0 5.5 6.0 normalized clock-to-output time supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature ( c) supply voltage (v) clock to output time vs. v cc 0.6 1.2 1.6 1.4 1.2 1.0 0.8 ? 55 125 normalized set-up time ambient temperature ( c) clock to output time vs. temperature 150 175 125 75 50 25 0.0 1.0 2.0 3.0 output sink current (ma) 0 100 output voltage (v) output sink current vs. output voltage 1.0 0.9 0.8 normalized i cc normalized i cc v cc =5.0v t a =25 c t a =25 c 0.6 0.6 1.02 1.00 0.98 0.96 0.94 0.92 025 5075 clock period (ns) 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 100 0.0 1000 t a =25 c v cc =4.5v t a =25 c f= f max 25 0.88 normalized supply current vs. clock period 4.0 1.4 1.2 1.0 0.8 1.6 1.4 1.2 1.0 0.8 ? 55 125 normalized set-up time 0.6 25 ambient temperature ( c) normalized set-up time vs. temperature 1.2 4.0 4.5 5.0 5.5 6.0 normalized clock-to-output time 0.4 supply voltage (v) normalized set-up time vs. supplyvoltage t a =25 c 1.0 0.8 0.6 normalized i cc 0.90 v cc =5.5v t a =25 c ordering information speed (ns) i cc (ma) ordering code package type package type operating range t sa t co 15 10 120 cy7c245a-15jc j64 28-lead plastic leaded chip carrier commercial 15 10 120 cy7c245a-15ji j64 28-lead plastic leaded chip carrier industrial 18 12 120 cy7c245a-18qmb q64 28-pin windowed leadless chip carrier military
cy7c245a document #: 38-04007 rev. *e page 8 of 13 f 18 12 120 cy7c245a-18wmb w14 24-lead (300-mil) windowed cerdip military 25 15 60 cy7c245a-25pc p13 24-lead (300-mil) molded dip commercial 25 15 90 cy7c245a-25jc j64 28-lead plastic leaded chip carrier commercial 35 20 60 cy7c245a-35wc w14 24-lead (300-mil) windowed cerdip commercial 120 cy7c245a-35qmb q64 28-pin windowed leadless chip carrier military ordering information (continued) speed (ns) i cc (ma) ordering code package type package type operating range t sa t co package diagrams figure 2. 24-lead (300-mil) cerdip d14 mil-std-1835 d- 9 config.a 51-80031-**
cy7c245a document #: 38-04007 rev. *e page 9 of 13 figure 3. 28-lead plastic leaded chip carrier j64 figure 4. 24-lead (300-mil) pdip p13 package diagrams (continued) 51-85001-*a 51-85013-*b
cy7c245a document #: 38-04007 rev. *e page 10 of 13 figure 5. 28-pin windowed leadless chip carrier q64 package diagrams (continued) mil?std?1835 c?4 51-80102-**
cy7c245a document #: 38-04007 rev. *e page 11 of 13 figure 6. 24-lead (300-mil) soic s13 package diagrams (continued) pin 1 id seating plane 0.597[15.163] 0.615[15.621] 1 12 13 24 * * * 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0 .026[0.66 0 ] 0.032[0.812] 0.004[0.101] part # s24.3 standard pkg. sz24.3 lead free pkg. min. max. note : 1. jedec std ref mo-119 2. body length dimension does not include mold protrusion/end flash,but mold protrusion/end flash shall not exceed 0.010 in (0.254 mm) per side 3. dimensions in inches 4. package weight 0.65gms does include mold mismatch and are measured at the mold parting line. 51-85025-*c
cy7c245a document #: 38-04007 rev. *e page 12 of 13 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 7. 24-lead (300-mil) windowed cerdip w14 all product and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued) 51-80086-** mil-std-1835 d-9 config. a
cy7c245a document #: 38-04007 rev. *e page 13 of 13 document history page document title: cy7c245a 2k x 8 reprogrammable registered prom document number: 38-04007 rev. ecn no. issue date orig. of change description of change ** 113863 3/6/02 dsg changed from sp ec number: 38-00074 to 38-04007 *a 118894 10/09/02 gbi updated ordering information *b 122248 12/27/02 rbi added power-up requirements to operating conditions information *c 130688 10/30/03 lsy added cy7c245a-15ji part number *d 130942 11/10/03 kkv minor change: soft copy became corrupted after sign off and before tech pubs. replaced with correct copy *e 499542 see ecn pci updated ordering information

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